data/HTML/_h_a_l_8h_source.html

00001
00018 #ifndef _HAL_H
00019 #define _HAL_H
00020
00021 /*
00022  **************************************************************
00023  * Defines, Macros and Typedefs
00024  **************************************************************/
00025 /*** Constant Macros ***/
00026 /* Default Yes and No defines */
00027 #ifndef TRUE
00028  #define TRUE (1u)
00029 #endif
00030 #ifndef CLEAR
00031  #define CLEAR (0u)
00032 #endif
00033
00034 #ifndef BITS_IN_BYTE
00035  #define BITS_IN_BYTE (8u)
00036 #endif
00037 #ifndef BYTES_IN_16
00038  #define BYTES_IN_16  (2u)
00039 #endif
00040 #ifndef BYTES_IN_32
00041  #define BYTES_IN_32  (4u)
00042 #endif
00043 #ifndef BIT_DEFINITION
00044  #define BIT_DEFINITION
00045  #define BIT0  (1u << 0u)
00046  #define BIT1  (1u << 1u)
00047  #define BIT2  (1u << 2u)
00048  #define BIT3  (1u << 3u)
00049  #define BIT4  (1u << 4u)
00050  #define BIT5  (1u << 5u)
00051  #define BIT6  (1u << 6u)
00052  #define BIT7  (1u << 7u)
00053  #define BIT8  (1u << 8u)
00054  #define BIT9  (1u << 9u)
00055  #define BIT10 (1u << 10)
00056  #define BIT11 (1u << 11)
00057  #define BIT12 (1u << 12)
00058  #define BIT13 (1u << 13)
00059  #define BIT14 (1u << 14)
00060  #define BIT15 (1u << 15)
00061  #define BIT16 (1u << 16)
00062  #define BIT17 (1u << 17)
00063  #define BIT18 (1u << 18)
00064  #define BIT19 (1u << 19)
00065  #define BIT20 (1u << 20)
00066  #define BIT21 (1u << 21)
00067  #define BIT22 (1u << 22)
00068  #define BIT23 (1u << 23)
00069  #define BIT24 (1u << 24)
00070  #define BIT25 (1u << 25)
00071  #define BIT26 (1u << 26)
00072  #define BIT27 (1u << 27)
00073  #define BIT28 (1u << 28)
00074  #define BIT29 (1u << 29)
00075  #define BIT30 (1u << 30)
00076  #define BIT31 (1u << 31)
00077 #endif
00078
00079 /* For interrupts */
00080 #define ISR_MAX_PRIORITY    (15u)
00081 #define ISR_UH_PRIORITY     (14u)
00082 #define ISR_VH_PRIORITY     (13u)
00083 #define ISR_HI_PRIORITY     (12u)
00084 #define ISR_MED_HI_PRIORITY (11u)
00085 #define ISR_MED_PRIORITY    (10u)
00086 #define ISR_MED_LO_PRIORITY (6u)
00087 #define ISR_LOW_PRIORITY    (4u)
00088 #define ISR_VL_PRIORITY     (3u)
00089 #define ISR_UL_PRIORITY     (2u)
00090 #define ISR_MIN_PRIORITY    (1u)
00091 #define ISR_INTC_PRIORITY   (0u)
00092
00093 /* Isr mapping for upper layers */
00094 #define CG147_WD2_ISR_CH    SOFT_CONFIG_FLAG_4
00095
00096 /* Addresses */
00097 #define RAM_BASE_ADDRESS    (0x40000000u)
00098
00099 /* DMA Channels (not related to the scheduler) */
00100 #define DEFAULT_ARRAY_COPY_CHANNEL                   (6u)
00101
00102 /* PIT Channels */
00103 #define PIT_SCHEDULING_CH     (0u)
00104 #define PIT_RESCHEDULE_CH     (1u)
00105 #define PIT_CH_DELAY          (3u)
00106
00107 /* Scheduler glue */
00108 //#define TICK_PERIOD           0.00006225 /* Time in sec */
00109 #define TICK_PERIOD           0.0001 /* Time in sec */
00110 //#define TICK_PERIOD           0.000125 /* Time in sec */
00111 //#define TICK_PERIOD           0.00025 /* Time in sec */
00112 #define SCHED_100US_PERIOD    ((uint32_t)(.0001 / TICK_PERIOD))
00113 #define SCHED_500US_PERIOD    ((uint32_t)(5u * SCHED_100US_PERIOD))
00114 #define SCHED_TICK_PERIOD     (uint32_t)(64000000 * TICK_PERIOD)
00115 #define RESCHED_TICK_PERIOD   (uint32_t)(64000000 * .000035)
00116
00117 /* PIT default Time-outs for 64MHz signal */
00118 #define PIT_1_SEC    (64000000u)
00119 #define PIT_1_MSEC   (64000u)
00120
00121 /* For special ADC Configurations */
00122 #define ADC_TAKE_1_2V_READING    ((uint8_t)0u)
00123 #define ADC_TAKE_TEMP_READING    ((uint8_t)1u)
00124
00125 /* ADC sensitivities */
00126 #define ADC_MAX_V        (3300000)
00127 #define ADC_TEMP_OFFSET  (1575000)
00128 #define ADC_TEMP_SENSITIVITY_PER_DEG (2400)
00129 #define ADC_SENSITIVITY  (uint16_t)(ADC_MAX_V / BIT10)
00130 #define ADC_TEMP_OFFSET_CTS (BIT10 * ADC_TEMP_OFFSET / ADC_MAX_V)
00131
00132 /* ADC0 dedicated channels */
00133 #define ADC_TO_AOUT_CH  ADC_CH12
00134
00135 /* Special use DMAs */
00136 #define ADC0_DMA_CH 8u
00137 #define ADC1_DMA_CH 9u
00138
00139 /* Special pins */
00140 #ifdef USE_ARD2_V1
00141 #define PIN_EN_FL      ('A'), ((uint8_t)2u)
00142 #define PIN_N_SYNC     ('A'), ((uint8_t)5u)
00143 #define PIN_N_SYS_RES  ('A'), ((uint8_t)15u)
00144 #define PIN_DSPI0_MISO ('C'), ((uint8_t)7u)
00145 #define PIN_DIS_AHP    ('A'), ((uint8_t)7u)
00146 #define PIN_DIS_ALP    ('A'), ((uint8_t)8u)
00147 #define PIN_DSPI0_SIN  ('C'), ((uint8_t)7u)
00148 #define PIN_N_CS_MON   ('C'), ((uint8_t)8u)
00149 #endif
00150 #ifdef USE_ARD2_V2
00151 #define PIN_EN_FL      ('A'), ((uint8_t)6u)
00152 #define PIN_N_SYNC     ('A'), ((uint8_t)5u)
00153 #define PIN_N_SYS_RES  ('A'), ((uint8_t)15u)
00154 #define PIN_DSPI0_MISO ('C'), ((uint8_t)7u)
00155 #define PIN_DIS_AHP    ('A'), ((uint8_t)7u)
00156 #define PIN_DIS_ALP    ('A'), ((uint8_t)8u)
00157 #define PIN_DSPI0_SIN  ('C'), ((uint8_t)7u)
00158 #define PIN_N_CS_MON   ('C'), ((uint8_t)8u)
00159 #endif
00160 #ifdef USE_ARD2_V3
00161 #define PIN_EN_FL      ('A'), ((uint8_t)6u)
00162 #define PIN_N_SYNC     ('A'), ((uint8_t)5u)
00163 #define PIN_N_SYS_RES  ('A'), ((uint8_t)15u)
00164 #define PIN_DSPI0_MISO ('C'), ((uint8_t)7u)
00165 #define PIN_DIS_AHP    ('B'), ((uint8_t)14u)
00166 #define PIN_DIS_ALP    ('B'), ((uint8_t)15u)
00167 #define PIN_DSPI0_SIN  ('C'), ((uint8_t)7u)
00168 #define PIN_N_CS_MON   ('C'), ((uint8_t)8u)
00169 #endif
00170
00171 /* Global 32-bit status errors */
00172 #define STATUS_DATA_TRANSFER_ERROR BIT12
00173 #define STATUS_SCHEDULER_PROBLEM BIT28
00174 #define STATUS_SM_STATE_ALREADY_EXECUTING BIT30
00175 #define STATUS_SM_INVALID_PREVIOUS_STATE  BIT31
00176
00177 /* Following defines address peripherals outside of the MCU */
00178 #ifdef USE_ARD2_V1
00179 #define CG147_SPI_CONFIG    DSPI0C4, BIT0
00180 #define CG147_SPI_CONFIG_EXT_1    DSPI0C6, BIT0
00181 #define CG147_SPI_CONFIG_EXT_2    DSPI0C7, BIT0
00182 #define CG147_SPI_CONFIG_EXT    DSPI0C6, DSPI0C7, BIT0
00183 #define CG147_SPI_CONFIG_MONITORING        DSPI0C4, (BIT0 | BIT6)
00184 #define CG147_SPI_CONFIG_EXT_MONITORING    DSPI0C6, DSPI0C7, (BIT0 | BIT6)
00185 #define CG147_ADC_CONFIG    ADC_MODULE_0, ADC_CH12
00186 #define MAIN_ACCELERO_SPI_CONFIG DSPI0C5, BIT3
00187 #define MIRANDA_SPI_CONFIG DSPI0C5, BIT2
00188 #endif
00189 #ifdef USE_ARD2_V2
00190 #define CG147_SPI_CONFIG    DSPI0C4, BIT0
00191 #define CG147_SPI_CONFIG_EXT_1    DSPI0C6, BIT0
00192 #define CG147_SPI_CONFIG_EXT_2    DSPI0C7, BIT0
00193 #define CG147_SPI_CONFIG_EXT    DSPI0C6, DSPI0C7, BIT0
00194 #define CG147_SPI_CONFIG_MONITORING        DSPI0C4, (BIT0 | BIT6)
00195 #define CG147_SPI_CONFIG_EXT_MONITORING    DSPI0C6, DSPI0C7, (BIT0 | BIT6)
00196 #define CG147_ADC_CONFIG    ADC_MODULE_0, ADC_CH12
00197 #define MAIN_ACCELERO_SPI_CONFIG DSPI0C5, BIT5
00198 #define MIRANDA_SPI_CONFIG DSPI0C5, BIT2
00199 #endif
00200 #ifdef USE_ARD2_V3
00201 #define CG147_SPI_CONFIG          DSPI0C4, BIT0
00202 #define CG147_SPI_CONFIG_EXT_1    DSPI0C6, BIT0
00203 #define CG147_SPI_CONFIG_EXT_2    DSPI0C7, BIT0
00204 #define CG147_SPI_CONFIG_EXT      DSPI0C6, DSPI0C7, BIT0
00205 #define CG147_SPI_CONFIG_MONITORING        DSPI0C4, (BIT0 | BIT6)
00206 #define CG147_SPI_CONFIG_EXT_MONITORING    DSPI0C6, DSPI0C7, (BIT0 | BIT6)
00207 #define CG147_ADC_CONFIG    ADC_MODULE_0, ADC_CH12
00208 #define MAIN_ACCELERO_SPI_CONFIG DSPI0C5, BIT5
00209 #define MIRANDA_SPI_CONFIG DSPI0C5, BIT4
00210 #endif
00211 /*** Function Macros ***/
00212 #ifndef N_ELEMENTS
00213  #define N_ELEMENTS(X)           (sizeof(X)/sizeof(*(X)))
00214 #endif
00215 /* Following can be used by drivers to clear ISR to them */
00216 #ifndef CLEAR_ISR_FLAG
00217 #define CLEAR_ISR_FLAG(XX)       INTC.SSCIR[XX].B.CLR = TRUE
00218 #endif
00219
00220 /* Preconfigured for delays */
00221 #define DELAY_SEC(xx)    u8fnDelay(PIT_1_SEC,  (xx))
00222 #define DELAY_MSEC(xx)   u8fnDelay(PIT_1_MSEC, (xx))
00223
00224 /*** Enums ***/
00225 enum INTERRUPT_LIST
00226 {
00227  SOFT_CONFIG_FLAG_0 = 0, SOFT_CONFIG_FLAG_1, SOFT_CONFIG_FLAG_2,
00228  SOFT_CONFIG_FLAG_3, SOFT_CONFIG_FLAG_4, SOFT_CONFIG_FLAG_5, SOFT_CONFIG_FLAG_6,
00229  SOFT_CONFIG_FLAG_7, RESERVED_1, ECSM_INT, DMA_COMBINED_ERROR_INT, DMA_0_INT,
00230  DMA_1_INT, DMA_2_INT, DMA_3_INT, DMA_4_INT, DMA_5_INT, DMA_6_INT, DMA_7_INT,
00231  DMA_8_INT, DMA_9_INT, DMA_10_INT, DMA_11_INT, DMA_12_INT, DMA_13_INT,
00232  DMA_14_INT, DMA_15_INT, RESERVED_2, SOFT_WATCHDOG_INT, RESERVED_3,
00233  STM_CH0_INT, STM_CH1_INT, STM_CH2_INT, STM_CH3_INT, RESERVED_4, ECSM_RAM_INT1,
00234  ECSM_RAM_INT2, RESERVED_5, RESERVED_6, RESERVED_7, RESERVED_8, SIU_IRQ_0,
00235  SIU_IRQ_1, SIU_IRQ_2, SIU_IRQ_3, RESERVED_9, RESERVED_10, RESERVED_11,
00236  RESERVED_12, RESERVED_13, RESERVED_14, ME_SAFE_MODE_INT,
00237  ME_MODE_TRANSITION_INT, ME_INVALID_MODE_INT, ME_INVALID_CONFIG_INT,
00238  RESERVED_15, RESET_GENERATION_MODULE_INT, XOSC_INT, RESERVED_16, PIT_CH0_INT,
00239  PIT_CH1_INT, PIT_CH2_INT, ADC0_EOC_INT, ADC0_ER_INT, ADC0_WD_INT, CAN0_ESR_INT,
00240  CAN0_WARNING_INT, CAN0_ESR_WAK_INT, CAN0_BUF_00_03_INT, CAN0_BUF_04_07_INT,
00241  CAN0_BUF_08_11_INT, CAN0_BUF_12_15_INT, CAN0_BUF_16_31_INT, RESERVED_17,
00242  DSPI0_FUF_INT, DSPI0_EOQF_INT, DSPI0_TFFF_INT, DSPI0_TCF_INT, DSPI0_RFDF_INT,
00243  LIN0_RXI_INT, LIN0_TXI_INT, LIN0_ERR_INT, ADC1_EOC_INT, ADC1_ER_INT,
00244  ADC1_WD_INT, RESERVED_18, RESERVED_19, RESERVED_20, RESERVED_21, RESERVED_22,
00245  RESERVED_23, RESERVED_24, RESERVED_25, RESERVED_26, DSPI1_FUF_INT,
00246  DSPI1_EOQF_INT, DSPI1_TFFF_INT, DSPI1_TCF_INT, DSPI1_RFDF_INT, LIN1_RXI_INT,
00247  LIN1_TXI_INT, LIN1_ERR_INT, RESERVED_27, RESERVED_28, RESERVED_29,
00248  RESERVED_30, RESERVED_31, RESERVED_32, RESERVED_33, RESERVED_34, RESERVED_35,
00249  RESERVED_36, RESERVED_37, RESERVED_38, DSPI2_FUF_INT, DSPI2_EOQF_INT,
00250  DSPI2_TFFF_INT, DSPI2_TCF_INT, DSPI2_RFDF_INT, RESERVED_39,
00251  RESERVED_40, RESERVED_41, RESERVED_42, RESERVED_43, RESERVED_44, RESERVED_45,
00252  RESERVED_46, PIT_CH3_INT, RESERVED_47, RESERVED_48, RESERVED_49, RESERVED_50,
00253  RESERVED_51, FLEX_FNEAIF_INT, FLEX_FNEBIF_INT, FLEX_WUPIF_INT, FLEX_PRIF_INT,
00254  FLEX_CHIF_INT, FLEX_TBIF_INT, FLEX_RBIF_INT, FLEX_MIF_INT, RESERVED_52,
00255  RESERVED_53, RESERVED_54, RESERVED_55, RESERVED_56, RESERVED_57, RESERVED_58,
00256  RESERVED_59, RESERVED_60, RESERVED_61, RESERVED_62, RESERVED_63, RESERVED_64,
00257  RESERVED_65, RESERVED_66, RESERVED_67, TIMER0_TC0IR_INT, TIMER0_TC1IR_INT,
00258  TIMER0_TC2IR_INT, TIMER0_TC3IR_INT, TIMER0_TC4IR_INT, TIMER0_TC5IR_INT,
00259  RESERVED_68, RESERVED_69, TIMER0_WTIF_INT, RESERVED_70, TIMER0_RCF_INT,
00260  TIMER1_TC0IR_INT, TIMER1_TC1IR_INT, TIMER1_TC2IR_INT, TIMER1_TC3IR_INT,
00261  TIMER1_TC4IR_INT, TIMER1_TC5IR_INT, RESERVED_71, RESERVED_72,
00262  RESERVED_73, RESERVED_74, RESERVED_75, PWM0_RF0_INT, PWM0_COF0_INT, PWM0_CAF0_INT,
00263  PWM0_RF1_INT, PWM0_COF1_INT, PWM0_CAF1_INT, PWM0_RF2_INT, PWM0_COF2_INT,
00264  PWM0_CAF2_INT, PWM0_RF3_INT, PWM0_COF3_INT, PWM0_CAF3_INT, PWM0_FFLAG_INT,
00265  PWM0_REF_INT, CTU0_MRS_INT, CTU0_T0_INT, CTU0_T1_INT, CTU0_T2_INT,
00266  CTU0_T3_INT, CTU0_T4_INT, CTU0_T5_INT, CTU0_T6_INT, CTU0_T7_INT,
00267  CTU0_FIFO1_INT, CTU0_FIFO2_INT, CTU0_FIFO3_INT, CTU0_FIFO4_INT, CTU0_ADC_INT,
00268  CTU0_ERR_INT, FLEXCAN_ESR_INT, FLEXCAN_WARNING_INT, FLEXCAN_ESR_WAK_INT,
00269  FLEXCAN_BUF_00_03_INT, FLEXCAN_BUF_04_07_INT, FLEXCAN_BUF_08_11_INT,
00270  FLEXCAN_BUF_12_15_INT, FLEXCAN_BUF_16_31_INT, RESERVED_76, DSPI3_FUF_INT,
00271  DSPI3_EOQF_INT, DSPI3_TFFF_INT, DSPI3_TCF_INT, DSPI3_RFDF_INT
00272 };
00273 enum INIT_ERRORS
00274 {
00275   PERIPHERALS_NOT_INITIALIZED = 1u, DEFAULT_OPERATION_MODES_NOT_LOADED,
00276   SWT_NOT_INITIALIZED, RUN_MODE_NOT_STARTED, PLL_ERROR
00277 };
00278 enum DELAY_ERRORS
00279 {
00280   PIT_SELECTED_CH_DOESNT_EXIST = 1u, PIT_TIMER_NOT_RUNNING
00281 };
00282 /*** TypeDefs ***/
00283 /* Used to configure ISR */
00284 #ifndef _INT_HANDLER_DECLARED
00285 #define _INT_HANDLER_DECLARED
00286 typedef void(*INTCInterruptFn)(void);
00287
00288 #endif
00289
00290 typedef struct
00291 {
00292   INTCInterruptFn pFn;
00293   uint16_t        u16ISRVector;
00294   uint8_t         u8Priority;
00295 } ISRConfig_t;
00296
00297 /*
00298  **************************************************************
00299  * Declarations
00300  **************************************************************/
00301 /*** Extern ***/
00302 extern const uint32_t cu32ADCConfig;
00303 extern const uint32_t cau32FCUConfig[];
00304 /*** Globals ***/
00305
00306 /*** Static Globals ***/
00307
00308 /*
00309  **************************************************************
00310  * Function Prototypes
00311  **************************************************************/
00312 /*
00313  ******************************************************************************
00314  *
00315  * Function:          u8fnMCUInit()
00316  *
00317  */
00330 uint8_t u8fnMCUInit(void);
00331 /*
00332  ******************************************************************************
00333  *
00334  * Function:          u8fnInitPeripherals()
00335  *
00336  */
00346 uint8_t u8fnInitPeripherals(void);
00347 /*
00348  ******************************************************************************
00349  *
00350  * Function:          u8fnInitInterrupts()
00351  *
00352  */
00361 void    vfnInitInterrupts(void);
00362 /*
00363  ******************************************************************************
00364  *
00365  * Function:          u8fnInitDSPI()
00366  *
00367  */
00376 void    vfnInitDSPI(void);
00377 /*
00378  ******************************************************************************
00379  *
00380  * Function:          vfnInitSCI()
00381  *
00382  */
00390 void    vfnInitSCI(void);
00391 /*
00392  ******************************************************************************
00393  *
00394  * Function:          vfnOutputPinInit()
00395  *
00396  */
00404 void vfnOutputPinInit(void);
00405 /*
00406  ******************************************************************************
00407  *
00408  * Function:          vfnInputPadInit()
00409  *
00410  */
00418 void vfnInputPadInit(void);
00419 /*
00420  ******************************************************************************
00421  *
00422  * Function:          vfnInitADC()
00423  *
00424  */
00436 void vfnInitADC(void);
00437 /*
00438  ******************************************************************************
00439  *
00440  * Function:          u8fnDelay()
00441  *
00442  */
00454 uint8_t u8fnDelay(const uint32_t cu32TimeBase, uint16_t u16Cycles);
00455 /*
00456  ******************************************************************************
00457  *
00458  * Function:          u8fnInitDMAMux()
00459  *
00460  */
00468 void vfnInitDMAMux(uint8_t* pu8DMAMuxSettings, uint8_t u8Size);
00469 /*
00470  ******************************************************************************
00471  *
00472  * Function:          u8fnRawADCToDegreesCelsius()
00473  *
00474  */
00481 uint8_t u8fnRawADCToDegreesCelsius(const uint16_t u16RawCounts);
00482 /*
00483  ******************************************************************************
00484  *
00485  * Function:          u8fnRawADCToOutput()
00486  *
00487  */
00494 uint8_t u8fnRawADCToOutput(const uint16_t u16RawCounts);
00495 /*
00496  ******************************************************************************
00497  *
00498  * Function:          vfnLaunchFCU()
00499  *
00500  */
00508 void vfnLaunchFCU(void);
00509 /*
00510  ******************************************************************************
00511  *
00512  * Function:          u8fnLaunchScheduler()
00513  *
00514  */
00524 uint8_t u8fnLaunchScheduler(const uint8_t cu8Enable);
00525 /*
00526  ******************************************************************************
00527  *
00528  * Function:          u8fnInitPostalService()
00529  *
00530  */
00541 uint8_t u8fnInitPostalService(const uint8_t cu8Enable);
00542 /*
00543  ******************************************************************************
00544  *
00545  * Function:          vfnTransferADCResults()
00546  *
00547  */
00559 void vfnTransferADCResults(uint8_t u8Instance, uint16_t* pu16Destination,
00560                            uint16_t u16Size);
00561 /*
00562  ******************************************************************************
00563  *
00564  * Function:          vfnEnterLowPowerMode()
00565  *
00566  */
00573 void vfnEnterLowPowerMode(void);
00574 /*
00575  ******************************************************************************
00576  *
00577  * Function:          vfnDefaultISR()
00578  *
00579  */
00586 static void vfnDefaultISR(void);
00587
00588 #endif /* _FILENAME_H */